Eh?
Unless it's a new meme that I've missed, I think you might be in the wrong section, lovey.
The nerds are next door but one, this room's for the kids.
How has this been achieved, electronically? Is there a "memory ready"-line for each bank, or something?
A typical memory IC has a set of address lines, one or more data line, a RD (read, active low - sometimes called OE for output enable) line to read from the address on the bus, a WR (write, active low) to write to an address, and a CS (chip select, active low) line to select this chip. The memory chip is only active if its CS pin is active. So if you have 12 chips on a bus, only one will have CS active at any one time - that will be the chip that's getting read or written to. The remaining 11 chips are all inactive at this time. 'Active low' means that when the pin is set to logic 0, it is active. 'Active high' means that the pin must be set to logic 1 to make the pin active.
You may have heard that computer circuits are either "off" or "on" - this is not actually the case at all. A memory chip's data bus pins have three states, not two. It can be logic 1, logic 0, or high impedance. A pin in the high impedance state is literally off. Logic 1 usually means that the pin is at Vcc voltage (for example +5 volts), and logic 0 usually means the pin is grounded (usually 0 volts). A chip that is not selected will have all its pins in high impedance state (i.e. "off"), meaning another chip connected to the bus can output the contents of a memory address on the bus.
DRAM has slightly different pins when selecting a memory address (RAS and CAS for row and column strobes) to static RAM (which just takes an address, exactly as the CPU presents it), but the principle is just the same - DRAM also has a chip select pin.
How has this been achieved, electronically? Is there a "memory ready"-line for each bank, or something?
If you are referring to "contended memory" as featured in ZX Spectrum design, it is actually the CPU which is temporarily halted (by holding the CLOCK line high), not the memory. Lots of details may be found in this thread.
Comments
Unless it's a new meme that I've missed, I think you might be in the wrong section, lovey.
The nerds are next door but one, this room's for the kids.
A typical memory IC has a set of address lines, one or more data line, a RD (read, active low - sometimes called OE for output enable) line to read from the address on the bus, a WR (write, active low) to write to an address, and a CS (chip select, active low) line to select this chip. The memory chip is only active if its CS pin is active. So if you have 12 chips on a bus, only one will have CS active at any one time - that will be the chip that's getting read or written to. The remaining 11 chips are all inactive at this time. 'Active low' means that when the pin is set to logic 0, it is active. 'Active high' means that the pin must be set to logic 1 to make the pin active.
You may have heard that computer circuits are either "off" or "on" - this is not actually the case at all. A memory chip's data bus pins have three states, not two. It can be logic 1, logic 0, or high impedance. A pin in the high impedance state is literally off. Logic 1 usually means that the pin is at Vcc voltage (for example +5 volts), and logic 0 usually means the pin is grounded (usually 0 volts). A chip that is not selected will have all its pins in high impedance state (i.e. "off"), meaning another chip connected to the bus can output the contents of a memory address on the bus.
DRAM has slightly different pins when selecting a memory address (RAS and CAS for row and column strobes) to static RAM (which just takes an address, exactly as the CPU presents it), but the principle is just the same - DRAM also has a chip select pin.
If you are referring to "contended memory" as featured in ZX Spectrum design, it is actually the CPU which is temporarily halted (by holding the CLOCK line high), not the memory. Lots of details may be found in this thread.