CPI emulation
I'm currently writing Sinclairean's emulation assembly for the CPI/CPD/CPIR/CPDR instruction group. Does anybody know what exactly the behavior of the last 5 T-states-long machine cycle is? Some docs state it's a memory write cycle, just like the LDI/LDD/LDIR/LDDR group (!)
Obviously, the CPxx group doesn't actually modify memory, but I'm wondering whether those docs are right at all, and if a real Z80 commits some sort of "dummy write" (for example, writing the same value into the same address pointed by HL, as a side effect of microcoding or whatever.)
If it is the case, I guess that write should be checked against contention.
Obviously, the CPxx group doesn't actually modify memory, but I'm wondering whether those docs are right at all, and if a real Z80 commits some sort of "dummy write" (for example, writing the same value into the same address pointed by HL, as a side effect of microcoding or whatever.)
If it is the case, I guess that write should be checked against contention.
Post edited by Madonna Mk 2 on
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The same goes for the extra 5 for the repeating varieties.
http://scratchpad.wikia.com/wiki/Contended_memory
Really interesting. The HL contents remain on the address bus for those 5T but the MREQ line is already inactive at that time. No actual read/write takes place, but the 48/128K's ULA contends anyway (it does not pay attention to MREQ) whereas the +2A/+3's does not.
http://zx-pk.ru/
Yep, which is why all those IR contended cycles have an effect also for the 48/128 machines. Which brings us to the one thing not made absolutely clear in the wiki - the final ir:1 contended cycle for LD I,A uses the old value of I, not the new value copied from A.