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DIY AY for 48k schematic

ArtemKuchinArtemKuchin
edited June 2012 in Hardware
Hello!

I can't seem to find a diy schematic for attaching AY to 48k so it gets 128k compatible sound. I see offers to sell ready made devices, but no tested and proven schematics for diy-ers.
Maybe i'm not looking good enough.
Anyone can help and point me in the right direction?
Post edited by ArtemKuchin on

Comments

  • Johan1973Johan1973
    edited June 2012
    http://s764.photobucket.com/albums/xx284/arioch1973/

    I uploaded those I get from Velesoft here, you can take a look at them. I tried to find them on his site, but where unable to locate them right now.
  • ArtemKuchinArtemKuchin
    edited June 2012
    Johan1973 wrote: »
    http://s764.photobucket.com/albums/xx284/arioch1973/

    I uploaded those I get from Velesoft here, you can take a look at them. I tried to find them on his site, but where unable to locate them right now.


    As i know that AY is clocked from separate crystal, so, only i looked at the pics with a separate crystal.

    The speed of AY is 1.7734MHz
    Looking at
    http://s764.photobucket.com/albums/xx284/arioch1973/?action=view¤t=ay-melodik.png
    i see that it has 3.57954 Mhz crystal devided by 2 with help of 74ls74, so we get 1.78977, which is a bit off.
    I don't understand what 74LS00 around crystal do. What are they for? Just a buffer?

    Everything else is pretty simple. Address selector, connectors. However, direct out connection is probably not the best way to go.
    It seems like this version
    http://zxspectrum48.i-demo.pl/AY_YM_interfaces.jpg
    has a opamp installed at the ouput.


    What i don't understand, why use a separate crystal, when i can get CPU clock from the BUS and devide by 2 like it is done in 128K speccy.
  • ShiruShiru
    edited June 2012
    You can use a divider. You can even get a YM2149F and use its built-in divider, so you can connect its CLK directly to the CPU's CLK line. As far as I remember, separate crystal was needed for devices that are connected to the expansion port on the original ZX Spectrum, there was some problem (either no CLK on the slot, or it is not stable as it used to make contention in the RAM).
  • ArtemKuchinArtemKuchin
    edited June 2012
    Shiru wrote: »
    You can use a divider. You can even get a YM2149F and use its built-in divider, so you can connect its CLK directly to the CPU's CLK line. As far as I remember, separate crystal was needed for devices that are connected to the expansion port on the original ZX Spectrum, there was some problem (either no CLK on the slot, or it is not stable as it used to make contention in the RAM).


    YM2149F is crazy 40 pin chip, too big :)
    I'd better built a devider.

    Thank you for informing me about CLK signal from the connector. Now i found:

    "The !CK signal, sometimes referred to as PHICPU is available on Lower Pin 8. This clock signal is generated by the ULA and is interrupted during contended memory access. This clock signal is inverted by a transistor switch to provide a clean clock edge for the Z80. "

    This totally sucks!

    It seems like this also happens inside. Since Z80 is clocked from ULA and ULA just stops CPU clock everywhere.
  • antoniovillenaantoniovillena
    edited June 2012
    Just take the OSC signal from the ULA (pin 39). It's uncontened. You will obtain a 14MHz signal. With a 4 bit counter (for example a 74XX161) you can obtain the 1.75Mhz signal that you want. Bit 0 in the output counter is a 7Mhz signal, bit 1 is 3.5MHz, so you need the bit 2 of the counter to obtain the desired 1.75Mhz.
  • ArtemKuchinArtemKuchin
    edited June 2012
    antoniovillena wrote: »
    Just take the OSC signal from the ULA (pin 39). It's uncontened. You will obtain a 14MHz signal. With a 4 bit counter (for example a 74XX161) you can obtain the 1.75Mhz signal that you want. Bit 0 in the output counter is a 7Mhz signal, bit 1 is 3.5MHz, so you need the bit 2 of the counter to obtain the desired 1.75Mhz.

    yes. good idea for a built-in version. or modify speccy, i can put osc signal from ula to an unused pin in the connector.
  • velesoftvelesoft
    edited June 2012
    Schematic of AY interface is here:
    http://hw.speccy.cz/ayinterface.html
  • ArtemKuchinArtemKuchin
    edited June 2012
    velesoft wrote: »
    Schematic of AY interface is here:
    http://hw.speccy.cz/ayinterface.html

    Thanks. That's the schematic i've chosen to implement from what Johan1973 uploaded.

    I really like the idea of dividing 14mhz from ula by 8 and feeding it into the AY chip. This will make it even more
    compact. Too bad AY cannot be SMD. Anyway, i ordered AY chip so i am just waiting for it now and doing the pcb.

    I have to play with this 14mhz clock because long wire from it to AY may not function well. Possible problem: no enoght drive from clock source or a lot of interference (the wire is an antenna after all).
  • ShiruShiru
    edited June 2012
    Actually there are SMD versions of the YM2149F, but they are really rare. These are YMZ284, it is SOJ16 (it has a single audio output, i.e. mono only), and YM3439, which is QFP44.
  • ArtemKuchinArtemKuchin
    edited June 2012
    Shiru wrote: »
    Actually there are SMD versions of the YM2149F, but they are really rare. These are YMZ284, it is SOJ16 (it has a single audio output, i.e. mono only), and YM3439, which is QFP44.

    Those are simple impossible to find.
    Interesting, did someone ever done a CPLD version of AY-3-8910/8912 ?

    One more question: Is AY output level good enough for feeding auto directly to tv audio-in?
  • WinstonWinston
    edited June 2012
    ArtemKuchin wrote: »
    "The !CK signal, sometimes referred to as PHICPU is available on Lower Pin 8. This clock signal is generated by the ULA and is interrupted during contended memory access. This clock signal is inverted by a transistor switch to provide a clean clock edge for the Z80. "

    Incidentally, just so no one goes down the same rabbit hole, I tried to use a PLL to regenerate the clock, but some of the contention cycles are too long for it to work reliably (or work reliably in a cost effective way, there's probably a circuit that can be built to do the job but it'd probably be far better just to either take the clock off the ULA direct, or find a way to do what you want where you don't depend on being synchronized with the CPU clock).

    (Explanation. You can use a PLL (phase locked loop) to regenerate clocks, or use in frequency multipliers, or a lot of other things in sync to some sort of master clock. The idea is the PLL synchronizes your oscillator with some source signal, in this case the Spectrum 3.5MHz clock. If there are missing bits to your signal, your oscillator will keep on going at 3.5MHz providing the clock signal. The trouble is if the signal you are synchronizing with is missing for too long, unless you have a really, really good oscillator, you'll drift out of sync by the time the master signal comes back. I could use a 74HC4046 PLL (which includes its own oscillator) to regenerate the Spectrum 3.5MHz clock, and be stable enough over some of the shorter contended cycles - but if there was too much contention going on my regenerated clock would get off far enough to not be pulled back into sync by the very few cycles before the next period of contention)
  • WinstonWinston
    edited June 2012
    ArtemKuchin wrote: »
    Those are simple impossible to find.
    Interesting, did someone ever done a CPLD version of AY-3-8910/8912 ?

    A CPLD won't be big enough.

    There are FPGA implementations though.
  • ShiruShiru
    edited June 2012
    There are few MCU-based (ATMega, C8051) AY emulators that could be used as a replacement.
  • ArtemKuchinArtemKuchin
    edited June 2012
    AFAIK Atmega emulation sounds horrible. But i never heard it personally.

    Interesting, how many gates real AY-3-8912 has comparing to around 20K used in FPGA version.
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