ZX Spectrum Clock Signal Restorer Circuit

edited June 2014 in Hardware
ZX Spectrum Clock Signal Restorer Circuit

The circuit below is an experimental circuit.
It has only been "tested" using SPICE simulation.
14314918236_bda00ac234_c.jpg
14151443520_e30f4af76f_c.jpg

If you wish to try this for real, ignore the round components marked V1 and V2. These are just voltage sources used by the SPICE.

Mark
Post edited by 1024MAK on

Comments

  • edited June 2014
    In what cases you are going to use this scheme?
  • edited June 2014
    Great to hear about this development! The proper buffering/signal conditioning of the CLK signal can improve the reliability of many popular interfaces. I'm looking forward any further news about it. :-)
  • edited June 2014
    Hi Mark,

    I think the BC547 is not a good choice. It is not a fast transistor. I also experimented with different circuits and as you wrote at the schematic, the delay was the problem.
    There are some very fast comparators at the market as the TL712 (the chip I used in the Harlequin for tape in). Such comparator could possibly be used. I myself use a simple FET inverter that until now works well with all of my Spectrums. Ben also tried this FET and found that there are situations that did not work well.

    Greets Ingo.
  • edited June 2014
    The resistor values that are used here did surprise me.
    I will do the static calculation in public, please do not hesitate to fill me in when I make a mistake....
    R1 plus R2 as voltage divider do set Q1b at 2.5V.
    Q1e will be ~ 0.6V lower (the usual semiconductor treshold), so will be 1.9V.
    So the voltage over R4 is 1.9V and the current through R4 is therefore 1.9 V/0.150 kOhm = 12.6 mA
    The same current goes through R3, causing a voltage drop of 12.6 mA/2.2 kOhm = 5.7 Volt which is more than the 5V source can deliver.

    Netto this means that without a pulsing signal Q1 will be saturated and the voltage at Q1c will be about 0V, and the current through Q1 will be 5V / 2.350 KOhm. Limited by the resitors only.
    Positive going pulses (behind C1) will not change that situation, and negative going pulses need a minimal amplitude of 2.5V to close Q1 to some degree and then get a higher voltage at Q1c.

    I happily admit that it is quite long ago since I learned to calculate transistor stages. Nevertheless the stabilising function of R4 seems redundant here and also the value of C2 looks rather small. I tend to think that IC1 is doing the real job in this set up.
    I also tend to think that R1,R2,D1 might be too much 'load' for the Spectrum's clock.
    For what it's worth guys!

    One of the problems seems to be differing DC offsets on the clock. Leveling these out (instead of cutting them away and causing a delay) seems to be the first problem to solve. Indeed let the fast comparator enter the stage...
  • edited June 2014
    ingo wrote: »
    I think the BC547 is not a good choice. It is not a fast transistor. I also experimented with different circuits and as you wrote at the schematic, the delay was the problem.
    The BC547C is indeed not as fast as some other (higher frequency) transistors. It was chosen because I have some in stock (or some BC548 or BC549C, I forget which) and because it is a transistor that is in the SPICE program that I am using.

    If I get time this week, I may try a test on my issue 1 Speccy.

    Mark
  • edited June 2014
    @ Roko

    I actually started with rather different values for the resistors. However, the values were changed when the SPICE showed that the circuit would not work in the way that I wanted. It is not designed to be a linear amplifier. It is suppose to overdrive and therefore "clip" the waveform.

    I had to reduce the value of R4 to ensure that the "logic low" voltage to the Schmitt inverter went below the TTL logic low level.

    You may be right about the loading on the ULA clock output. I am aware of this issue. I need to conduct some tests to see what kind of load the ULA output can tolerate.

    This is at the moment, just experimenting with ideas. One way to deal with variable or inconsistent unwanted DC levels in an AC system, is to use a coupling capacitor. But of course, the coupling capacitor introduces additional problems: a change of waveform shape and a delayed signal. I then thought about the single switching transistor that Sinclair used between the ULA and the Z80 CPU.

    By adding a single transistor stage ahead of a TTL Schmitt inverter, I was thinking that it may be possible to "square up" the clock signal for expansion devices that do not need a fully synchronized clock signal.

    If you look at the waveform picture that I posted, you will see that in the SPICE simulation, the transistor (Q1) does a surprisingly good job of squaring up the signal with the deliberately poor "input" clock that I got the SPICE to generate.

    Of course in practice, how well it will work is another matter.

    In the waveform diagram:
    Green = simulated poor input clock signal
    Dark blue = schmitt inverter output
    Red = Q1 base signal
    Cyan = Q1 collector signal (input to schmitt inverter)
    Magenta = Q1 emitter signal

    Mark
  • edited June 2014
    1024MAK wrote: »
    This is at the moment, just experimenting with ideas. Mark
    Yes, please continue.

    I thought that balancing out a DC component which is present in the input signal, was a rather normal thing to do for an OpAmp. But a search on internet did not bring result, to my surprise...
  • edited June 2014
    Hi Roko,
    roko wrote: »
    I thought that balancing out a DC component which is present in the input signal,
    why do you think to have to do this? Using a capacitor to decouple DC offset works perfectly. The capacitor has to be that big to bypass the time of missing clock while contention is present.

    Greets Ingo.
  • edited June 2014
    ingo wrote: »
    why do you think to have to do this?
    Hi Ingo,

    I was thinking along the lines of how negative going video sync's can be 'taken' from a composite signal and finally added again, exactly as they were, to the amplified video part.
    I have no clear picture in my head, and could not find a relevant schematic.
    Part of the idea was the brainwave that the DC component could be 'restored' at any suitable level afterwards. Maybe even automaticly to suit all Versions.

    Roelof.
  • edited June 2014
    Recently I was experimenting with the following circuit to make an acceptable clock signal for the DivMMC EnJOY! and the Spectranet interface (combined with SPECTRA):
    CLK_circuit.png
    A friend of mine gave me the idea to use inverters for clock signal "amplification". Originally he recommended 74HC04, but I had only 74LS04 at home and the electronic part shops are closed at the weekends... :smile: What do you think about that?

    According to my tests it worked well with my ISSUE 1 Spectrum and made me possible to use DivMMC EnJOY! and Spectranet connected through a SPECTRA interface. It improved the situation with my ISSUE3B Spectrum+. This Spectrum suffering from a significant DC offset on the CK signal at the edge connector. Without this circuit it didn't worked at all if I connected DivMMC EnJOY! through the SPECTRA interface. With this circuit the success rate was 60%. It turned out later, that the NEC CPU has some issues and it didn't worked well with Spectranet. I've replaced the Z80 and it fixed the operation with Spectranet. Unfortunately I've accidentally killed my DivMMC EnJOY!, so I can't test it after the CPU replacement. I've tested this circuit with an ISSUE2 and an ISSUE4B Spectrum (DivMMC EnJOY! + SPECTRA) and it loaded the test program every time without errors (20/20).

    Pictures on the clock signals and tests are here:
    http://gigant.chem.elte.hu/ZXSpectrum/CK_circuit/
  • edited June 2014
    From the issue 1 trace, it looks like there's more of a delay than in Mark's solution.

    However the proof of the pudding is in the eating, and if everything's working that's the best proof :)

    Using a HC part as in the 128K machines might make the solution bulletproof of course.

    B
    The Spectrum Resuscitation Thread - bringing dead Spectrums back to life
    zx-diagnostics - Fixing ZX Spectrums in the 21st Century (wiki)
    Sinclair FAQ Wiki
  • edited June 2014
    Other possible parts to try:
    74HCU04 CMOS unbuffered inverter
    74HC14 schmitt trigger inverter

    Of course, the trick is to come up with a circuit that is compatible with as many Spectrum issues and models as possible (ideally, all of them).

    This means the circuit has to cope with a good square wave circuit, a misshapen square wave that looks like a triangle waveform and signals that are outside normal TTL levels (logic low too high, logic high too low, or both!). And, with minimum edge/signal delay and trying to keep the mark-space ratio equal.

    Mark
  • edited June 2014
    Thank you for the comments! I will try the HC04 and the HC14 parts as soon as I will get them. First of all I have to repair the DivMMC EnJOY!... Without that I can't test the circuit. Unfortunately I will be away next week from these beauties, but I will continue testing as soon as I will have the parts and repaired the DivMMC EnJOY! interface.

    The output was not a symmetrical square wave. Mainly the rising edge was about at the right place and the falling edge was delayed. Somehow both the DivMMC EnJOY! and the Spectranet "accepted" that. I tried 5 different machines and all were working except my first Spectrum+... :( It looks like, that the position of the rising edge is more important... I'm not sure in it, but it looks like...

    There was an interesting phenomenon during the tests... I plugged the small circuit together on a breadboard using relatively long wires. In my first test circuit I didn't used the "pulldown" on the output. When the scope was connected to the circuit, everything worked fine, but as I removed the probe from the output it didn't worked at all... :confused: ... Finally I tried to connect only one "end" of the probe. As I connected the ground pole to it it worked again. After that I decided to use a 10k pulldown. It was only an intuition... I'm a chemist so I don't these things in details. Do you have some idea why it has happened? What did I wrong with the measurement?
  • edited June 2014
    That will be the capacitance of the 'scope lead...

    Mark
  • edited June 2014
    ULA uses signal levels compatible with TTL logic. If your DivMMC uses a CMOS inverter for signal CK/, this scheme will not work. You can try to fix this by connecting to the inverter input pullup of consistently linked 1k resistor and inductance 47mkH.
  • edited June 2014
    I've found just a Schmitt trigger (74HCT series) will work perfectly with the machines in question (although I think it's probably worth having a simple FET stage at the front to be useful since I think the toastrack 128K clock doesn't even make TTL levels).

    With just a Schmitt trigger inverter you get a pretty clean output (on a decent PCB).

    cleanclk.png
  • edited June 2014
    I would simply take this:

    file.php?id=2678

    Why transistors if you want a digital signal ?
    The 74LVC1G08 is a tiny small IC, 2 SMD resistors and 1 capacitor - thats it.
    Maybe one more for the power supply (10uF SMD 0805).
    This is a cheap but powerful solution and gives a clock with up to +/- 32mA.
    Time delay is approx. 2 ns. :-)

    I wouldn't use a Schmitt Trigger for this.
    The switch point is about 1.4V when using 3V supply voltage and should be near 2.35V when using 5V.

    I am not sure how bad the signal really is - maybe you can omit all other components except a block capacitor for supply voltage.
  • edited June 2014
    Hi Pokemon,
    PokeMon wrote: »
    Why transistors if you want a digital signal ?
    It's because the /clk signal coming from the Spectrums edge connector is made to be inverted by a single transistor to have the same phase like the CPU. Inside the 48k and the heatsink version there is also a transistor inverting the /clk signal for the CPU itself. The /clk signal from ULA is coupled using 1 kOhm to the base of a npn transistor this way a big load is at the /clk output of the ULA. Therefore the level drops to be lower than 2V at its maximum.

    All interfaces that uses the /clk signal normally invert it using als a very fast transistor (fT >= 500 MHz) similar to that inside the spectrum so there is similar delay by this stage. Using any other circuitry one has to make sure to operate at low levels and not adding undesired delay. Unfortunately there are big differences between the 48k / 128k heatsink computers and the Amstrad versions +2, +2A/B, +3. The Amstrad versions have real TTL level at the /clk output because inside the computer there is not a transistor but a fast TTL gate to invert the /clk. SO there is no big load at the /clk ULA output.

    The circuits described in this thread are thought to be inserted between the /clk line of the edge connector and the inverter input of external interfaces. This is in most cases not the best way because the delay of the additional level improoving stage is added to that of the inverter at the external interface. It is better to modify the inverter of the interface or to substitute the transistor inside the 48k / 128k hetasink computer by a TTL inverter (or a FET transistor inverter) as done in the +2 (and later) computers.
    PokeMon wrote: »
    I am not sure how bad the signal really is - maybe you can omit all other components except a block capacitor for supply voltage.
    The problem is to make a circuitry working with the low levels of a 48k /128k /clk output as well as with the TTL level output of the +2 and later.

    Ingo.

    BTW: Your picture link from tlienhard is dead.
  • edited June 2014
    Thanks for your hints. About the picture - I tried to attach it here but it is not allowed to upload pictures here on the forum. This is quite uncommon and makes additional work to the users. But not my problem now. You might see the picture only when logged in into tlienhard or maybe with my account only. :lol:

    So the approach is to have a good clk signal without inverting it - all other proposals here do it either not. What's speaking against transistors is that a single transistor doesn't match the game and you need additional equipment (resistors and capacitors) to get it fast and (!) need a second to invert it again. Even a hf transistor is not fast if you use it in saturated mode which is common for save and fast digital applications.

    So in fact my advise is to use just a single gate non inverting (there aren't really simple buffers provided but many inverters) like 74LVC1G08 or 74LVC1G32. They are really fast (I use them in my video interfaces for preparing monochrome video signals), cheap, small and need no additional components. Just a 5 pin SMD IC - maybe a block capacitor, thats all. If you put a double diode like BAV99 in the 5V supply to bring it to 3.5V level they will deliver an excellent TTL signal outside and input level is TTL compatible as well and will switch more or less exactly at 1.4V level like the LS technology but with a very powerful output. That's one more reason why I don't use LS, HC or better HCT in such designs. The totempole outputs deliver fine 24mA (3 V level) or 32mA (5V level).

    So for these kind of applications there is not too much sense to use transistors, resistors and capacitors - except you have them and don't know what to do else with them. :)

    Cheers.
  • edited June 2014
    PokeMon wrote: »
    I would simply take this:

    file.php?id=2678

    Why transistors if you want a digital signal ?
    The 74LVC1G08 is a tiny small IC, 2 SMD resistors and 1 capacitor - thats it.
    Maybe one more for the power supply (10uF SMD 0805).
    This is a cheap but powerful solution and gives a clock with up to +/- 32mA.
    Time delay is approx. 2 ns. :-)

    I wouldn't use a Schmitt Trigger for this.
    The switch point is about 1.4V when using 3V supply voltage and should be near 2.35V when using 5V.

    I am not sure how bad the signal really is - maybe you can omit all other components except a block capacitor for supply voltage.

    For those who did not understand, I repeat again: series 74LVC designed for CMOS input levels and will not work with the input signals are TTL level. Suitable any TTL series: LS, ALS, AS, F, HCT, ACT, AHCT.

    The problem of signal amplitude CK/ does not exist - this is a fiction! Signal CK/ has the correct TTL level.
  • edited June 2014
    Black_Cat wrote: »
    For those who did not understand, I repeat again: series 74LVC designed for CMOS input levels and will not work with the input signals are TTL level. Suitable any TTL series: LS, ALS, AS, F, HCT, ACT, AHCT.

    Well - in that point you are definetly wrong.
    See Texas Instruments "Low Voltage Logic designer's guide":
    www.ti.com/lit/ml/scba010/scba010.pdf

    Or see the picture:
    lvc.jpg

    The low voltage series was developped to meet the TTL specifications exactly. Anyway they are not specified upwards 3.3V Vcc but if you increase the power voltage they behave like CMOS levels. That's really a great compromise. If you supply 3.3V they behave exactly like TTL , accept TTL input level and even the output level of maximum 3.3V is inside the TTL specifications.
    :-)

    And by the way - all inputs of LVC family are 5V tolerant. So no problem when interfacing to 5V TTL - this is handeled internally.
  • edited June 2014
    PokeMon, 74LVC you can use if they Vcc= 3,3V. With Vcc= 5V cannot be used.
  • edited June 2014
    Black_Cat wrote: »
    PokeMon, 74LVC you can use if they Vcc= 3,3V. With Vcc= 5V cannot be used.

    Sorry but (at least partly) wrong again. ;-)

    The "little logic gates" (a subspecification of LVC series with many 6 to 8 pin devices, containing single or double gates/register/flipflops) do support 5V operation. Even the bigger LVC can be used with 5V operation as well, but the behaviour is not as well documented as for the little logic devices (transition level for example). The LL devices are fully specified for this operation area.

    lvc2.jpg

    lvc3.jpg

    By the way, NXP calls them picogates, little logic maybe a registered trademark from Texas Instruments. :)
    Technical summary

    LVC logic devices are specified over 1.65Vto3.6V (standard) or 1.65Vto5.5V (PicoGate). With a balanced output drive of 24mA and typical propagation delay of 4ns, the LVC family includes buffers/line drivers, transceivers, gates, analog switches and translators .

    Over voltage tolerant I/O, source termination resistor, bus hold and power OFF are some of the advanced features of these devices making them ideal for parallel interface applications.

    LVC products are available in SO, TSSOP, PicoGate and innovative leadless MicroPak and DQFN packages for PCB space saving. NXP's LVC products are fully specified from -40Cto125C.
    http://www.nxp.com/products/logic/family/LVC/#description
  • edited June 2014
    Hi Pokemon,

    the low amplitude of the /clk signal of only about 1.0 ... 1.5V (from minimum to maximum) will not fit the demands of the logic chips you recommend, which need at the input (0.3 ... 0.7)*Vcc which is a minimal amplitude of 0.4 Vcc = 2 V at Vcc=5V.

    A comparator with a small hysteresis is better to use or a FET with a small threashold voltage.

    Greets Ingo.
  • edited June 2014
    ingo wrote: »
    Hi Pokemon,

    the low amplitude of the /clk signal of only about 1.0 ... 1.5V (from minimum to maximum) will not fit the demands of the logic chips you recommend, which need at the input (0.3 ... 0.7)*Vcc which is a minimal amplitude of 0.4 Vcc = 2 V at Vcc=5V.

    A comparator with a small hysteresis is better to use or a FET with a small threashold voltage.

    Greets Ingo.

    Hi Ingo,

    my advise was to use it in the 3.3V voltage range where it exactly meets TTL specifications, see picture above. In fact the transistion voltage is exactly at 1.4 to 1.5V with (nearly) no hysteresis. So this would be perfect for the /CLK signal described above. :)

    And I don't use 3.3V voltage regulators, a double diode of BAV99 would do the job (non-schottky of course).
  • edited June 2014
    ingo wrote: »
    the low amplitude of the /clk signal of only about 1.0 ... 1.5V (from minimum to maximum) will not fit the demands of the logic chips you recommend, which need at the input (0.3 ... 0.7)*Vcc which is a minimal amplitude of 0.4 Vcc = 2 V at Vcc=5V.


    Signal CK/ (green) conforms to TTL levels:14151443520_e30f4af76f_c.jpg
  • edited June 2014
    Err. before you chaps get too carried away, keep in mind that this waveform image:

    14151443520_e30f4af76f_c.jpg

    is a computer generated simulation (as I said in the first post, a SPICE simulation).

    The V(clock_in) {green coloured} waveform is just an approximation of what a distorted ULA clock output may be like, based on the information available to me at the time (as I do not own a Sinclair 128k + "toastrack" to test with). NONE of the waveforms in the above picture are taken from real hardware. The clock signal from a Sinclair 128k + "toastrack" could be worse, or may be slightly better.

    As the clock output from some Spectrums does not meet TTL logic level specifications, the idea in the first post was to see if a simple transistor stage could be used to "clean-up" the signal. The inverter following the transistor was put in to see if a further stage would create an even better output waveform.

    Of course, I am happy for people to come up with other designs and ideas.

    This is an experimental circuit. It may be possible to use such a circuit in-between a Spectrum and an interface, but because of the processing of the clock signal and the propagation delay, that may affect the performance of interfaces where the timing is critical.

    Mark
  • edited June 2014
    I never measured this signal in my 48k version but the above proposal with the little logic and 3.3V takes even signals out of TTL window with "high" voltages below 2.0V. This is maybe a design failure in the spectrum or - as Clive would say "a feature". :D
  • edited June 2014
    PokeMon wrote: »
    So the approach is to have a good clk signal without inverting it - all other proposals here do it either not. .

    Generally you DO want to invert it. The clock signal at the edge connector is inverted with respect to what the CPU sees. The clock signal at the edge connector is not the CPU clock, but the ULA clock. The CPU gets an inverted version of the CPU clock. If your application cares about being in phase with the CPU, you need to invert it.

    The other thing is the ULA clock is not even really TTL, it's not even close to a square wave (more of a shark fin wave) and on the 128K toast rack machines it doesn't even reach TTL spec voltages.
  • edited June 2014
    Winston wrote: »
    Generally you DO want to invert it. The clock signal at the edge connector is inverted with respect to what the CPU sees. The clock signal at the edge connector is not the CPU clock, but the ULA clock. The CPU gets an inverted version of the CPU clock. If your application cares about being in phase with the CPU, you need to invert it.

    The other thing is the ULA clock is not even really TTL, it's not even close to a square wave (more of a shark fin wave) and on the 128K toast rack machines it doesn't even reach TTL spec voltages.


    Well - just read (more) carefully.
    That was all we are talking about here in the last days.

    If somebody want to improve the signal internally he wouldn't invert the signal to the edge connector because all interfaces connected to and using the clock would wonder what's going on with the good old speccy. :lol:

    Second - it is clear to all discussion members here, that the clock signal is not good and not full ttl compatible. But exactly that was the reason for this thread - or why should a clock signal restorer circuit (see threads title) been ever used when the clock signal is perfect ?? :o
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