The PCB is compatible with standard Sinclair IF2. But I did't try if fit in a cartridge case, probably not. But you can change the PCB design to fit in the case.
No you can't, because a QFP chip, doesn't fit in there.
The other chips have SOIC versions, but there are many (3) :) so it will not fit, due to not enough surface area.
I like the simplicity of the design, however, it was clearly designed to be setup to a specific ROM bank and then LOCKED to that BANK.
From the schematics, I found that It uses memory accesses of the form "00111111 111111LA" to select the Bank.
Where "L" bit is used to LOCK selection register (6 bit flip-flop) of further changes indefinitely (until reset) when set to 1.
"A" is used to serially pump/populate selection register with data.
This works great, if you are running bank selection code from RAM.
However, trying this serial selection is probably a nightmare to control (almost impossible), if you want to run your control code from ROM, since bank will be switching due to the serial input, while running the pumping code :P
So I'm assuming, what the Menu ROM does, is copy the selection code into RAM, and then run from there.
Nice neat design, but doesn't work for my target case.
TIP: taking into account target usage of this design (set and lock), it can be changed to just load the bank register in one go, by using the lower 5 address bits directly, and lock on first access, or use an extra bit to lock (as is used know). Using last 32 or 64 ROM addresses is no problem for the target usage.
This would take the same hardware, but would make running control code from ROM as easy as from RAM.
You've learned very quickly my design. Thank you for your interest. Yes, it can be changed just for load the bank register, but in this case the usable ROM is more reduced. With this bank logic you only miss 4 bytes of 16384. With paralel load you miss 64 bytes. Multiply this by 3 for loading snapshots.
But yes, parallel load is possible. For example I did it with iFrom (another interface I've designed) and the code for snapshot is shared with conditional assembly. You can see the code is simpler with the iFrom. I put a link for the iFrom:
You've learned very quickly my design. Thank you for your interest. Yes, it can be changed just for load the bank register, but in this case the usable ROM is more reduced. With this bank logic you only miss 4 bytes of 16384. With paralel load you miss 64 bytes. Multiply this by 3 for loading snapshots.
But yes, parallel load is possible. For example I did it with iFrom (another interface I've designed) and the code for snapshot is shared with conditional assembly. You can see the code is simpler with the iFrom. I put a link for the iFrom:
Ok, your usage case is slightly different, since you require almost full 16KB (-1 byte), so that you can load 48K snapshots using 3 banks only.
Fair enough. since it requires you to change banks 3 times, before locking.
I also noticed that ROMCS, is locked down to VCC, making the Cartridge always selected, even after you load the softwre/game/sna into memory.
This limits compatible software, to the ones that do not use the Spectrum ROM.
Maybe you could do a simple change, to detect, if you lock on Bank 0 (your Menu, I presume), to disable ROMCS. NOTE: I'm assuming that Menu ROM is always included.
This would make all software compatible, since Cartridge could be turned off, after loading.
I also noticed that ROMCS, is locked down to VCC, making the Cartridge always selected, even after you load the softwre/game/sna into memory.
This limits compatible software, to the ones that do not use the Spectrum ROM.
It don't suppose problem, because when I load 3 banks from ROM into RAM then I switch to a slot bank with the same 48K ROM. Of course we miss one ROM because we only access 32 banks instead 32+1 (if we can disable ROMCS) but I have space reduced because I use discrete logic (3 chips). If I use GAL or CPLD It will a good idea.
Another idea, that seems easy to implement with a GAL or CPLD.
Detect two consecutive accesses to address #0000 and #FFFF, followed by an access to a memory position, setup by I/R register, to be used as input.
In terms of implementation, a single bit (Flip-Flop) can keep state that we accessed this information.
It only has to keep the result of an OR of all bits (for #0000) and AND of all bits (for #FFFF).
So we need one bit for detect #0000, another to detect #FFFF.
Then we need another bit (or just use the second bit, and direct AND result), to mark that special condition has been triggered, then use another bit or two to keep it for an extra instruction (delay control), to wait for I/R data input.
This can be implemented with a simple LDI or LDD instruction with correctly set HL and DE registers, followed by another instruction like LD A,(HL) or similar to provide the input data.,
It's a fairly uncommon pattern, easy to detect, but easy to trigger on purpose.
Thinking about it, it can be even easier to implement, and keeping an uncommon pattern, if the two consecutive addresses are just #0000.
Simplifies implementation, since we can just chain two or 3 flipflops together, that keep the last results of OR all address lines. When all flip-flops are zero, we just load current address which is our control input.
There is one minor drawback, which is: LDI will try to write to address #0000.
If I'm not mistaken, address lines are protected with resistors, but that is only between CPU and keyboard/ULA. External interface (where ROM cartrige is connected) is not protected, as far as I remember
I'll have to check schematics to be sure.
From all the version schematics I have checked (2, 3a, 3b, 4a, 4b, 5 and 6a) all have pull-ups on the Data Lines, and resistors between CPU data lines and ULA data lines, but no protection resistors between CPU and external interface.
I have been searching for some EEPROM or FLASH with the following conditions:
- 5V
- 200ns access time (read) or less (ideal less than 100ns, to support 7Mhz Z80s)
- 512K bytes x8 bit (4 MBit)
- Parallel Interface
-TSOP, TTSOP or Flatpack Package
- as cheap as possible :)
And the options I found so far, are not that many:
- Atmel AT28C040-20FI, it's on the 200ns border, and I would prefer something less than 100ns
- SST39SF040, exists in 55 or 70ns, which is great. (SST39SF040-70-4C-WHE or SST39SF040-70-4I-WHE)
Do you guys know a few more, that comply with above requirements ?
There is one minor drawback, which is: LDI will try to write to address #0000.
If I'm not mistaken, address lines are protected with resistors, but that is only between CPU and keyboard/ULA. External interface (where ROM cartrige is connected) is not protected, as far as I remember
I'll have to check schematics to be sure.
The resistors are not there for protection. They are just used as a cheap way of separating the data bus into two sections. Done so the Z80 CPU can access ROM or "upper" RAM while the ULA gets screen data.
There is no protection on any of the Z80 CPU address, control or data lines that go to the edge-connector.
! Standby alert !
“There are four lights!”
Step up to red alert. Sir, are you absolutely sure? It does mean changing the bulb!
Looking forward to summer in Somerset later in the year :)
There is one minor drawback, which is: LDI will try to write to address #0000.
If I'm not mistaken, address lines are protected with resistors, but that is only between CPU and keyboard/ULA. External interface (where ROM cartrige is connected) is not protected, as far as I remember
I'll have to check schematics to be sure.
The resistors are not there for protection. They are just used as a cheap way of separating the data bus into two sections. Done so the Z80 CPU can access ROM or "upper" RAM while the ULA gets screen data.
There is no protection on any of the Z80 CPU address, control or data lines that go to the edge-connector.
Mark
The resistors, work like protection (current limiting), because if two chips force/output on the same data lines, the resistor between both sides prevents a surge in current, that would burn the chip(s).
Resistor limits current when both sides have opposite signals (1/0; VCC/GND), and as a side effect allows both sides to have distinct values.
There is one minor drawback, which is: LDI will try to write to address #0000.
If I'm not mistaken, address lines are protected with resistors, but that is only between CPU and keyboard/ULA. External interface (where ROM cartrige is connected) is not protected, as far as I remember
I'll have to check schematics to be sure.
The resistors are not there for protection. They are just used as a cheap way of separating the data bus into two sections. Done so the Z80 CPU can access ROM or "upper" RAM while the ULA gets screen data.
There is no protection on any of the Z80 CPU address, control or data lines that go to the edge-connector.
Mark
The resistors, work like protection (current limiting), because if two chips force/output on the same data lines, the resistor between both sides prevents a surge in current, that would burn the chip(s).
Resistor limits current when both sides have opposite signals (1/0; VCC/GND), and as a side effect allows both sides to have distinct values.
Resistors will limit a fault current, absolutely right. But Sinclair did not use them for that reason. As I said, he used them to allow the two sections of the data bus to work separately when needed. Further, in the Amstrad machines resistors are not used, with chips being used for bus isolation and separation instead..
Some designs of chip output drivers can withstand a short circuit. This is partly due to the internal resistance of the output driver. Depending on the technology used, the time that the chip can sustain a short circuit varies. In practice, a lot of chips can survive a brief (at least one Z80 CPU cycle where the CPU clock is 3.5MHz approx.) short circuit. This is because the heat build up is limited and does not reach damaging levels in such a short time.
! Standby alert !
“There are four lights!”
Step up to red alert. Sir, are you absolutely sure? It does mean changing the bulb!
Looking forward to summer in Somerset later in the year :)
I have been searching for some EEPROM or FLASH with the following conditions:
- 5V
- 200ns access time (read) or less (ideal less than 100ns, to support 7Mhz Z80s)
- 512K bytes x8 bit (4 MBit)
- Parallel Interface
-TSOP, TTSOP or Flatpack Package
- as cheap as possible :)
And the options I found so far, are not that many:
- Atmel AT28C040-20FI, it's on the 200ns border, and I would prefer something less than 100ns
- SST39SF040, exists in 55 or 70ns, which is great. (SST39SF040-70-4C-WHE or SST39SF040-70-4I-WHE)
Do you guys know a few more, that comply with above requirements ?
The trouble is that parallel flash is going the way of the dodo. The SST39F040 would be my go-to parallel NOR flash chip for speccy stuff now based mostly on the property of actually being manufactured :(
Yes, it seems seems serial is what the industry is going for, at least for flash memories, apparently because these are usually used just to keep settings or Iinitialization parameters.
Anyway, if someone knows any other chip that fits mentioned requirements, please do speak out.
Thanks
P.S.
A good source for references could be new/recent add-ons to vintage/retro computers that you might have access to.
I have my design almost finished (doing the PCB now),
However, now I see that I can probably make it writable by software running on ZX Spectrum, with some extra hacking on Logic device (still have a few Flip-flops free).
So I'm investigating Flash memory write cycle, to see what I need to change to support it.
Current format/pattern for operation on address lines is:
ADDR, ADDR, ADDR, I/R, dataAddr
However, checking exactly for any address 3 times in sequence, would require 16 bits to keep the last address for comparison, plus a few bits to count sequential repetitions.
Obviously this is overkill for a small Programmable Logic Device (PLD), in terms of pins and flip-flop resources.
Engineering is a discipline, where we have to balance competing factors and strive to find a good compromise.
In this regard, since we can't keep the last address, we must use a fixed one, which means that our bank switch code will also be fixed at the specific address.
However, using a fixed address, would also require us to check 16 bits, but since we do not have enough pins, this would imply an external logic chip, like an AND-8 or OR-8 to shrink the number of inputs required from PLD.
However, due to space constrains, an extra chip is probably not feasible.
So, we will probably have to check fewer bits, which in turn, will make the target ADDR more probable of being matched in consecutive bus address, since we are not checking all bits.
NOTE:This will allow for Bank switching code to be place in more than one location which is a small advantage.
Nonetheless, 3 consecutive addresses that will match even ignoring a few bits, is a good compromise, if the extra chip cannot be fitted.
An alternative possibility is to eventually implement an AND-N or OR-N, using Diodes and a resistor, which are probably easier to fit within the PCB layout.
Software implementation will be something like the following:
;InputParams: A = Command, [E = Command Param], BC = Addr
;Output A = data
LD I, A ; Set command
LD A,E ; Save command param
LD HL, ADDR
LD E,L
LD D,H
DEC BC ; Compensate for CPI increment
SUB 3 ; Compensate for CPI[s][/s] and ADDR instruction R increments
LD R,A ; Setup command Param
CPI ; Critical set of instructions to force required bus addr pattern
ADDR LD A,(BC)
WARNING: This block must be run only with interrupts disabled, so that "I" register can be safely changed.
I/R registers, can be saved (before calling this routine) and restored just after. while interrupts are disabled.
In theory, similar code can be used to write command control codes to FLASH memory, assuming PLD correctly controls flash memory Output Enable (OE) and Write Enable (WE), based on some control bit(s) from I/R, and using code like:
;InputParams: A = Command, [E = Command Param], BC = Addr
;Output A = data
LD I, A ; Set command
LD A,E ; Save command param
EX AF,AF'
LD HL, ADDR
LD E,L
LD D,H
DEC BC ; Compensate for CPI increment
SUB 4 ; Compensate for EX, CPI and ADDR instruction R increments
LD R,A ; Setup command Param
EX AF,AF'
CPI ; Critical set of instructions to force required bus addr pattern
ADDR LD (BC),A
Still have to route 2 capacitors, and add GND and VCC Zones, but still have some room to spare. So it's definitely possible to fit it in the original ROM-Cartridge board form factor.
With some patience, it's even possible to add an extra logic chip (NAND-8), by first moving PLD little bit up(top), if there is a need to match more address lines.
P.S.
Meanwhile I spotted an error in schematic, that would make 3/4 of the ROM unavailable (A14, A15) would allways be 0,0 :(
Fixing that next.
You may find a 74HCT688 digital comparator more useful for address decoding. It can match 8 inputs to another 8 inputs. So you can select (via tracks/pads) which address lines you want to be logic 0 and which to be logic 1.
! Standby alert !
“There are four lights!”
Step up to red alert. Sir, are you absolutely sure? It does mean changing the bulb!
Looking forward to summer in Somerset later in the year :)
You may find a 74HCT688 digital comparator more useful for address decoding. It can match 8 inputs to another 8 inputs. So you can select (via tracks/pads) which address lines you want to be logic 0 and which to be logic 1.
Mark
Yes, it's a nice idea, specially when you have space to set some Micro DIP Switches or similar, since it allows it to be configurable.
However, space here is at a premium and a 74688 requires at 20 pin package, while a 7430 or similar, requires only a 14 pin package. A comparator is also usually slower then a gate, but in this case, the difference is of no concern.
Good tip, but probably won't fit on the left over space..
3 - Added a VCC and GND plane. (also helps build some capacitance, besides capacitors).
4 - Added 4 status LEDs (ON, CE, OE, WR ) and 4 Resistors (603) on back side (facing user), since its' height should fit (0.6mm of 1.0mm available), and could be seen in a non black case, or a black case with holes, and/or transparent label.
But even if they don't fit, they are just for debugging, useful for developers (which might not use a case), but they are completely optional, so, they can be left out, which will guarantee case will fit.
Next prototype, generate logic expressions and make sure it works :D
Apparently, ATF22V10C (Atmel SPLD ) doesn't allow to reuse Flip-Flops that are not being used for output pins.
i.e. you either use the Flip-Flops for output, or you can't use them :(
I was counting on being able to use them, but apparently this isn't possible.
Luckily, Atmel has a pin compatible version, to ATF22V10C, named ATF750C, which is a "Complex PLD" (CPLD), instead of a "Simple PLD" (SPLD).
These provide what they call "buried Flip-Flops", which can be used even when you use the pins, since they have twice the number of Flip-Flops, one regular and one "buried" Flip-Flop for each I/O pin.
However there are two set backs:
- In general this chip is more or less double price of the previous one.
- Although it is listed in datasheet in TSSOP package, I can't seem to find a seller for the TSSOP version of it.
Not even Atmel has it listed :(
If some of you know were to find them (ATF750C-10XU or ATF750CL-15XU), please report back.
Actually my mistake was to search for ATF750C-15XU when only low power version exists (ATF750CL-15XU).
For prototyping, I'm going to order DIP or PLCC versions of the chips, since they are easier to program (no need for an adapter on EEPROM programmer) and I can use a prototype board instead of a specifically manufactured board.
I still need some form of edge connector to connect to ZX Spectrum.
Comments
No you can't, because a QFP chip, doesn't fit in there.
The other chips have SOIC versions, but there are many (3) :) so it will not fit, due to not enough surface area.
I like the simplicity of the design, however, it was clearly designed to be setup to a specific ROM bank and then LOCKED to that BANK.
From the schematics, I found that It uses memory accesses of the form "00111111 111111LA" to select the Bank.
Where "L" bit is used to LOCK selection register (6 bit flip-flop) of further changes indefinitely (until reset) when set to 1.
"A" is used to serially pump/populate selection register with data.
This works great, if you are running bank selection code from RAM.
However, trying this serial selection is probably a nightmare to control (almost impossible), if you want to run your control code from ROM, since bank will be switching due to the serial input, while running the pumping code :P
So I'm assuming, what the Menu ROM does, is copy the selection code into RAM, and then run from there.
Nice neat design, but doesn't work for my target case.
TIP: taking into account target usage of this design (set and lock), it can be changed to just load the bank register in one go, by using the lower 5 address bits directly, and lock on first access, or use an extra bit to lock (as is used know). Using last 32 or 64 ROM addresses is no problem for the target usage.
This would take the same hardware, but would make running control code from ROM as easy as from RAM.
But yes, parallel load is possible. For example I did it with iFrom (another interface I've designed) and the code for snapshot is shared with conditional assembly. You can see the code is simpler with the iFrom. I put a link for the iFrom:
http://www.va-de-retro.com/foros/viewtopic.php?f=50&t=4554
Ok, your usage case is slightly different, since you require almost full 16KB (-1 byte), so that you can load 48K snapshots using 3 banks only.
Fair enough. since it requires you to change banks 3 times, before locking.
I also noticed that ROMCS, is locked down to VCC, making the Cartridge always selected, even after you load the softwre/game/sna into memory.
This limits compatible software, to the ones that do not use the Spectrum ROM.
Maybe you could do a simple change, to detect, if you lock on Bank 0 (your Menu, I presume), to disable ROMCS. NOTE: I'm assuming that Menu ROM is always included.
This would make all software compatible, since Cartridge could be turned off, after loading.
Just an idea.
It don't suppose problem, because when I load 3 banks from ROM into RAM then I switch to a slot bank with the same 48K ROM. Of course we miss one ROM because we only access 32 banks instead 32+1 (if we can disable ROMCS) but I have space reduced because I use discrete logic (3 chips). If I use GAL or CPLD It will a good idea.
Nice work around :)
Detect two consecutive accesses to address #0000 and #FFFF, followed by an access to a memory position, setup by I/R register, to be used as input.
In terms of implementation, a single bit (Flip-Flop) can keep state that we accessed this information.
It only has to keep the result of an OR of all bits (for #0000) and AND of all bits (for #FFFF).
So we need one bit for detect #0000, another to detect #FFFF.
Then we need another bit (or just use the second bit, and direct AND result), to mark that special condition has been triggered, then use another bit or two to keep it for an extra instruction (delay control), to wait for I/R data input.
This can be implemented with a simple LDI or LDD instruction with correctly set HL and DE registers, followed by another instruction like LD A,(HL) or similar to provide the input data.,
It's a fairly uncommon pattern, easy to detect, but easy to trigger on purpose.
Simplifies implementation, since we can just chain two or 3 flipflops together, that keep the last results of OR all address lines. When all flip-flops are zero, we just load current address which is our control input.
If I'm not mistaken, address lines are protected with resistors, but that is only between CPU and keyboard/ULA. External interface (where ROM cartrige is connected) is not protected, as far as I remember
I'll have to check schematics to be sure.
- 5V
- 200ns access time (read) or less (ideal less than 100ns, to support 7Mhz Z80s)
- 512K bytes x8 bit (4 MBit)
- Parallel Interface
-TSOP, TTSOP or Flatpack Package
- as cheap as possible :)
And the options I found so far, are not that many:
- Atmel AT28C040-20FI, it's on the 200ns border, and I would prefer something less than 100ns
- SST39SF040, exists in 55 or 70ns, which is great. (SST39SF040-70-4C-WHE or SST39SF040-70-4I-WHE)
Do you guys know a few more, that comply with above requirements ?
There is no protection on any of the Z80 CPU address, control or data lines that go to the edge-connector.
Mark
Repair Guides. Spanish Hardware site.
WoS - can't download? Info here...
former Meulie Spectrum Archive but no longer available :-(
Spectranet: the TNFS directory thread
! Standby alert !
“There are four lights!”
Step up to red alert. Sir, are you absolutely sure? It does mean changing the bulb!
Looking forward to summer in Somerset later in the year :)
The resistors, work like protection (current limiting), because if two chips force/output on the same data lines, the resistor between both sides prevents a surge in current, that would burn the chip(s).
Resistor limits current when both sides have opposite signals (1/0; VCC/GND), and as a side effect allows both sides to have distinct values.
Some designs of chip output drivers can withstand a short circuit. This is partly due to the internal resistance of the output driver. Depending on the technology used, the time that the chip can sustain a short circuit varies. In practice, a lot of chips can survive a brief (at least one Z80 CPU cycle where the CPU clock is 3.5MHz approx.) short circuit. This is because the heat build up is limited and does not reach damaging levels in such a short time.
Mark
Repair Guides. Spanish Hardware site.
WoS - can't download? Info here...
former Meulie Spectrum Archive but no longer available :-(
Spectranet: the TNFS directory thread
! Standby alert !
“There are four lights!”
Step up to red alert. Sir, are you absolutely sure? It does mean changing the bulb!
Looking forward to summer in Somerset later in the year :)
Not a single geek out there ?
The trouble is that parallel flash is going the way of the dodo. The SST39F040 would be my go-to parallel NOR flash chip for speccy stuff now based mostly on the property of actually being manufactured :(
Anyway, if someone knows any other chip that fits mentioned requirements, please do speak out.
Thanks
P.S.
A good source for references could be new/recent add-ons to vintage/retro computers that you might have access to.
However, now I see that I can probably make it writable by software running on ZX Spectrum, with some extra hacking on Logic device (still have a few Flip-flops free).
So I'm investigating Flash memory write cycle, to see what I need to change to support it.
However, checking exactly for any address 3 times in sequence, would require 16 bits to keep the last address for comparison, plus a few bits to count sequential repetitions.
Obviously this is overkill for a small Programmable Logic Device (PLD), in terms of pins and flip-flop resources.
Engineering is a discipline, where we have to balance competing factors and strive to find a good compromise.
In this regard, since we can't keep the last address, we must use a fixed one, which means that our bank switch code will also be fixed at the specific address.
However, using a fixed address, would also require us to check 16 bits, but since we do not have enough pins, this would imply an external logic chip, like an AND-8 or OR-8 to shrink the number of inputs required from PLD.
However, due to space constrains, an extra chip is probably not feasible.
So, we will probably have to check fewer bits, which in turn, will make the target ADDR more probable of being matched in consecutive bus address, since we are not checking all bits.
NOTE:This will allow for Bank switching code to be place in more than one location which is a small advantage.
Nonetheless, 3 consecutive addresses that will match even ignoring a few bits, is a good compromise, if the extra chip cannot be fitted.
An alternative possibility is to eventually implement an AND-N or OR-N, using Diodes and a resistor, which are probably easier to fit within the PCB layout.
Software implementation will be something like the following:
;InputParams: A = Command, [E = Command Param], BC = Addr ;Output A = data LD I, A ; Set command LD A,E ; Save command param LD HL, ADDR LD E,L LD D,H DEC BC ; Compensate for CPI increment SUB 3 ; Compensate for CPI[s][/s] and ADDR instruction R increments LD R,A ; Setup command Param CPI ; Critical set of instructions to force required bus addr pattern ADDR LD A,(BC)WARNING: This block must be run only with interrupts disabled, so that "I" register can be safely changed.
I/R registers, can be saved (before calling this routine) and restored just after. while interrupts are disabled.
In theory, similar code can be used to write command control codes to FLASH memory, assuming PLD correctly controls flash memory Output Enable (OE) and Write Enable (WE), based on some control bit(s) from I/R, and using code like:
;InputParams: A = Command, [E = Command Param], BC = Addr ;Output A = data LD I, A ; Set command LD A,E ; Save command param EX AF,AF' LD HL, ADDR LD E,L LD D,H DEC BC ; Compensate for CPI increment SUB 4 ; Compensate for EX, CPI and ADDR instruction R increments LD R,A ; Setup command Param EX AF,AF' CPI ; Critical set of instructions to force required bus addr pattern ADDR LD (BC),AStill have to route 2 capacitors, and add GND and VCC Zones, but still have some room to spare. So it's definitely possible to fit it in the original ROM-Cartridge board form factor.
With some patience, it's even possible to add an extra logic chip (NAND-8), by first moving PLD little bit up(top), if there is a need to match more address lines.
P.S.
Meanwhile I spotted an error in schematic, that would make 3/4 of the ROM unavailable (A14, A15) would allways be 0,0 :(
Fixing that next.
Mark
Repair Guides. Spanish Hardware site.
WoS - can't download? Info here...
former Meulie Spectrum Archive but no longer available :-(
Spectranet: the TNFS directory thread
! Standby alert !
“There are four lights!”
Step up to red alert. Sir, are you absolutely sure? It does mean changing the bulb!
Looking forward to summer in Somerset later in the year :)
Yes, it's a nice idea, specially when you have space to set some Micro DIP Switches or similar, since it allows it to be configurable.
However, space here is at a premium and a 74688 requires at 20 pin package, while a 7430 or similar, requires only a 14 pin package. A comparator is also usually slower then a gate, but in this case, the difference is of no concern.
Good tip, but probably won't fit on the left over space..
2 - Routed Capacitor tracks.
3 - Added a VCC and GND plane. (also helps build some capacitance, besides capacitors).
4 - Added 4 status LEDs (ON, CE, OE, WR ) and 4 Resistors (603) on back side (facing user), since its' height should fit (0.6mm of 1.0mm available), and could be seen in a non black case, or a black case with holes, and/or transparent label.
But even if they don't fit, they are just for debugging, useful for developers (which might not use a case), but they are completely optional, so, they can be left out, which will guarantee case will fit.
Next prototype, generate logic expressions and make sure it works :D
Apparently, ATF22V10C (Atmel SPLD ) doesn't allow to reuse Flip-Flops that are not being used for output pins.
i.e. you either use the Flip-Flops for output, or you can't use them :(
I was counting on being able to use them, but apparently this isn't possible.
Luckily, Atmel has a pin compatible version, to ATF22V10C, named ATF750C, which is a "Complex PLD" (CPLD), instead of a "Simple PLD" (SPLD).
These provide what they call "buried Flip-Flops", which can be used even when you use the pins, since they have twice the number of Flip-Flops, one regular and one "buried" Flip-Flop for each I/O pin.
However there are two set backs:
- In general this chip is more or less double price of the previous one.
- Although it is listed in datasheet in TSSOP package, I can't seem to find a seller for the TSSOP version of it.
Not even Atmel has it listed :(
If some of you know were to find them (ATF750C-10XU or ATF750CL-15XU), please report back.
Thanks
I did the mistake of only searching for ATF750C-10XU.
Apparently ATF750CL-X15XU is more common and available.
I also found it on Alibaba.
Once again, thank you for the heads up.
For prototyping, I'm going to order DIP or PLCC versions of the chips, since they are easier to program (no need for an adapter on EEPROM programmer) and I can use a prototype board instead of a specifically manufactured board.
I still need some form of edge connector to connect to ZX Spectrum.
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From top to Bottom{/b]:
NOTE: What distinguishes if it's a ROM or RAM read are address lines (A15,A14) = (0,0) or not, respectively.
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