... by fiddling with Z80's clock signal, as opposed to inserting a ... start with the 14 MHz. signal that ULA takes as input ... Xilinx XC9536 to generate the clock signal, it may work but you ... 's clock output isn't a clean 3.58 MHz. signal (so ...

... a previously divided clock - remember that ULA's clock output isn't ... a clean 3.58 MHz. signal (so ... /> As for the ULA's clock output, it actually generates significantly ... Xilinx XC9536 to generate the clock signal, it may work but you ...

... ]As for the ULA's clock output, it actually generates significantly ... (probably more than a Z80 clock input would draw but still ... you feed it to Z80 clock input (perhaps a simple resistor ... . feed it to Z80 as clock signal)...

... (probably more than a Z80 clock input would draw but still ... .

But a Z80 clock pin is a FET input ... that you'll get a clock signal that's out of spec ...

... thing would be to check clock signal, you'd need logic tester ...

... real spectrum by stopping the clock signal to the z80. While the ... , when finished it starts the clock signal again. I think it does ...

... real spectrum by stopping the clock signal to the z80. While the ... , when finished it starts the clock signal again. I think it does ... by f**king with its clock signal) when there's a conflict ...

... work with the Spectrum's clock signal... but perhaps someone with more ...

... work with the Spectrum's clock signal... but perhaps someone with more ...

... it's not getting a clock signal (which comes from the ULA ...

Love the last line:

The Z80 clock signal is brought out to the edge connector (Whoops). :lol:

[QUOTE=MrCheese;592221]Love the last line:

The Z80 clock signal is brought out to the edge connector (Whoops). :lol:[/QUOTE]

I didn't understand that bit, why is it whoops? The 48k brought !CK to the edge connector too...

... , I check the ULA's clock signal. This is difficult without scope ... say whether you have a clock signal or not). When you have ... safe assumption ULA has a clock signal.

Then it's ...

... , I check the ULA's clock signal. This is difficult without scope ... say whether you have a clock signal or not). When you have ... safe assumption ULA has a clock signal.

Then it's ...

... it powers the clock for the CPU (no clock = no activity, of ... on a 48K). Check the clock signal if you can and look ...

... is used, you have a clock signal that runs independent with respect ... to other clock signals in the system. Read ...

... for informing me about CLK signal from the connector. Now i ... found:

"The !CK signal, sometimes referred to as PHICPU ... on Lower Pin 8. This clock signal is generated by the ULA ... memory access[/I][/B]. This clock signal is inverted by a transistor ...

... on Lower Pin 8. This clock signal is generated by the ULA ... memory access[/I][/B]. This clock signal is inverted by a transistor ... some source signal, in this case the Spectrum 3.5MHz clock. If ... at 3.5MHz providing the clock signal. The trouble is if the ...

The original 128k motherboard has NO clock signal on the edge connector.

[url]http://k1.dyndns.org/Vintage/Sinclair/86/ZX%20Spectrum%2B%20128K%20%28Spanish%29/PCBs/PCB%202.1%20Spanish%20rear.jpg[/url]

... Spectrum's clock signal (and therefore keep the board's clock signal going during ... ULA basically suspends the CPU clock during contention, but my oscillator ... going on and not enough clock cycles then things tended to ...

Can anyone recommend me a very small 14 Mhz oscillator so I can a clock signal to my AY chip?

... a much better quality composite signal than from the 1889 circuit ... leave the Z80 without a clock signal during and after the reset ...

... leave the Z80 without a clock signal during and after the reset ... /> Also you can use "DONE" signal from FPGA to reset Z80 ...

... - in other words, regenerating the clock signal which goes away during contention ... , then go and test the clock recovery with a real machine ...

... - in other words, regenerating the clock signal which goes away during contention ... , then go and test the clock recovery with a real machine ...

... the absence of the clock signal to feed this shift ... to the removal of the clock in contention.

So every received clock edge places the PLL ... register.
When the clock goes missing for more ... and shifted by the PLL clock instead.

...

... to the CPLD.
Reset signal is buffered by the 74HCT14 ... global reset pin.

Clock signal is also buffered and inverted ... jumper to operate ROMCS (global clock pins can also be used ...

... higher use of CMOS the signal edges are much sharper, with ... interesting harmonics (the 3.5MHz clock signal coming out of the 48K ...

[QUOTE=bverstee;673130]By the way, the reason I was in the understanding that the Xilinx and Altera series CPLD's use different development approach/language, was that one of the CPLD files for the K-Mouse Turbo I got from Velesoft contains equations like ...

... network, only C4, on the clock signal circuit is electrolytic.
Anyway ...