... more sense having the /RD signal inverted, so that it stays ... well. Let's name that signal /Xout.

The " ... 3 gets the /Xout signal that we covered above.
clock signal, pin 4 is the /PRE ... and is used as the clock for the D-type ...

... be the cause of no clock signal[/QUOTE]

It could ...

... tester. I get nice sinus signal of 14MHz.
I have ... /> I'am still getting no clock signal on ULA pin 39 or ... when there is no 3MHz clock i should check ULA pin ...

... tried to look at the clock signal. (I don't have a ... show any difference in the clock signal at the CLK pin of ... the different CPU types. The clock signal at the ULA was sinusoid ...

... reflections (the 48K's clock signal is a sawtooth, and ... going part of the signal is ended up getting ... to falsely see another clock transition). The 47pF ... use of the CLK signal until decoding the instruction ... is getting a bad clock signal, you will at least ...

... if the interface uses the clock signal), along with the Spectranet?
clock line maybe?

[I ...

... likely a problem with the clock signal getting reflected when it ... Sinclair put the unamplified inverted clock signal on the edge connector, ... the much better and amplified clock signal after it's been ... other stuff to the clock signal which isn't ideal.< ...

... connecting other stuff to the clock signal which isn't ideal.[/QUOTE ...

... it's dead or the clock signal isn't getting to it ...

... between +5V and the inverted clock signal, 8B on the edge connector ...

... to the very-very weak clock signal (1.46V)
[IMG]http ...

... circuits on the toastrack's clock signal, with an LM358.


No usable signal at the output either.

... pull-up resistor on the clock signal, needed for most toastracks which ... have a very weak clock signal.
You are the first ... Imre Jakli from Hungary about clock signals on 48K models: he ... measured the clock signals with different ULA's ...

Not only the clock signal intensity, but the ... "high level" of the clock signal is 2.88V which is ... 6 or 6C001E-7 the clock signal became "normal". It ... nicer screenshots of the clock signal, so I share you ... ! and we suspected the clock signal problem. I've made ...

... bad clock signal with significant DC offset (760-800mV) or the clock signal was ...

I modified the other ISSUE4A. Now it is working, but not reliably (70-80%). Unfortunately it suffers from a rather high (760mV) DC offset in the clock signal, that may cause these type of problems.

... from the theoretical 5V... The clock signal at the edge connector comes ... at the CPU clock pin. Not counting the "nice" signal shape... :o ... highest level of the HIGH signal was only 3.04V, there ... TTL logic.

These signal level only depend on the ...

... possible to "square up" the clock signal for expansion devices that do ... not need a fully synchronized clock signal.

If you look ... :
Green = simulated poor input clock signal
Dark blue = schmitt inverter ...

... circuit to make an acceptable clock signal for the DivMMC EnJOY! ... idea to use inverters for clock signal "amplification". Originally he recommended ... DC offset on the CK signal at the edge connector. ... />
Pictures on the clock signals and tests are here ...

... Toastrack switch "shifts" the CK signal a little bit "up". If ... the "low" part of the clock signal.

As far ... Amstrad made Spectrums the CK signal at the edge connector is ... experimented a little with a clock signal amplifier circuit. These tests were ...

... taken from real hardware. The clock signal from a Sinclair 128k + " ... .

As the clock output from some Spectrums does ... to "clean-up" the signal. The inverter following the transistor ... of the processing of the clock signal and the propagation delay, ...

... to have a good clk signal without inverting it - all other ... want to invert it. The clock signal at the edge connector is ... what the CPU sees. The clock signal at the edge connector is ... inverted version of the CPU clock. If your application cares about ...

... want to invert it. The clock signal at the edge connector is ... the CPU sees. The clock signal at the edge connector is ... discussion members here, that the clock signal is not good and not ... thread - or why should a clock signal restorer circuit (see threads title ...

... , or the quality of the clock signal :D

... 'd bet that the CPU clock signal is interfering with your picture ... that some sort of periodic signal is being superposed to the ... video signal.

Second: these ... This means that the superimposed signal has a frequency of half ...

TR3 buffers the clock signal generated by the ULA (including wait states) to the CPU. You won't see any benefit changing this unless it's broken :D

B

... CPU is controlled from the clock signal, which comes from the ULA ... crystal to generate the "master" clock.

Does the black ...

... CPU is controlled from the clock signal, which comes from the ULA ... crystal to generate the "master" clock.

Does the black ...

... 'scope would show if the clock signal to the Z80 CPU was ...

... the ULA halt the CPU clock in the normal way if ... the DMA controller from that clock line, or do you have ... access with the CPU's clock signal and to set up each ...