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32. The Zilog Z80 microprocessor instruction set reference
The reference of the Z80 mnemonics have been included for the sake of a quick guide during program analysation, optimising and debugging. This reference was used intensively during the design phase of Intuition.
Mnemonic Notation:
r specifies any one of the registers: A,
B, C, D, E, H, L.
(HL) specifies the contents of memory at the location addressed
by HL.
n specifies a 16 bits expression in the
range (0 to 255).
nn specifies a 8 bits expression in the range
(0 to 65535), low byte first.
d specifies a 8 bits displacement value
in the range (-128 to 127).
(nn) specifies the contents of memory at the location addressed
by nn address.
b specifies an expression in the range
(0 to 7).
e specifies a one-byte expression in the
range (-126 to 129).
cc specifies the condition flag :
Z (Zero), NZ (Not Zero)
C (Carry), NC (Not Carry)
P (Plus), M (Minus)
PO (Parity Odd), PE
(Parity Even)
qq specifies any one of the register pairs:
BC, DE, HL or AF.
ss specifies any one of the register pairs:
BC, DE, HL or SP.
pp specifies any one of the register pairs:
BC, DE, IX or SP.
rr specifies any one of the register pairs:
BC, DE, IY or SP.
s specifies any of r, n, (HL), (IX+d)
or (IY+d).
dd specifies any one of the register pairs:
BC, DE, HL or SP.
m specifies any of r, (HL), (IX+d) or
(IY+d).
Flagregister notation:
? Changed functionally according to operation. * Flag not affected. X Flag is set randomly by operation. 0 Flag is reset. 1 Flag is set. V Flag signals overflow by operation. P Flag signals even parity.The symbol 'V' in the Flags column displays the P/V flag. The leftmost flag bit, the Sign flag, represents bit 7 - the rightmost bit, the Carry flag, represents bit 0. Bit 5 and 3 (with the '.' symbol) are not used, but are set randomly by the processor during execution of various instructions.
The numbers in the instruction opcode column represents the binary representation of the byte opcode from bit 0 to 7 (total of eight bits).
When no hexadecimal number is displayed several opcodes are generated from the bit pattern.
The index registers registers IX and IY are fully represented with the IY register example (IX only varies with the 1. opcode DDh).
GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
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Mnemonic Symbolic Flags (bit 7-0) Instruction Number Number of Number of Comments
operation S Z . H . V N C opcode of bytes M cycles T states
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DAA Converts accum. ? ? X ? X P * ? 00 100 111 (27h) 1 1 4 Decimal
contents into adjust
packed BCD format accumulator
CPL A <- NOT A * * X 1 X * 1 * 00 101 111 (2Fh) 1 1 4 Complement
(1. complement) accumulator
NEG A <- 0 - A ? ? X ? X V 1 ? 11 101 101 (EDh) 2 2 8 Negate
(2. complement) 01 000 100 (44h) accumulator
CCF CY <- NOT CY * * X X X * 0 ? 00 111 111 (3Fh) 1 1 4 Complement
Carry flag
SCF CY <- 1 * * X 0 X * 0 1 00 110 111 (37h) 1 1 4 Set Carry
flag
NOP No operation * * X * X * * * 00 000 000 1 1 4
HALT CPU halted * * X * X * * * 01 110 110 (76h) 1 1 4
DI IFF <- 0 * * X * X * * * 11 110 011 (F3h) 1 1 4
EI IFF <- 1 * * X * X * * * 11 111 011 (FBh) 1 1 4
IM 0 Set int. mode 0 * * X * X * * * 11 101 101 (EDh) 2 2 8
01 000 110 (46h)
IM 1 Set int. mode 1 * * X * X * * * 11 101 101 (EDh) 2 2 8
01 010 110 (56h)
IM 2 Set int. mode 2 * * X * X * * * 11 101 101 (EDh) 2 2 8
01 011 110 (5Eh)
IFF = Interrupt enable flip-flop
8-BIT LOAD GROUP
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Mnemonic Symbolic Flags (bit 7-0) Instruction Number Number of Number of Comments
operation S Z . H . V N C opcode of bytes M cycles T states
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LD r, r' r <- r' * * X * X * * * 01 <r> <r'> 1 1 4 r:
LD r, n r <- n * * X * X * * * 00 <r> 110 2 2 7 000 C
-- <n> --- 001 B
010 E
LD r,(HL) r <- (HL) * * X * X * * * 01 <r> 110 1 2 7 011 D
LD r,(IX+d) r <- (IX+d) * * X * X * * * 11 011 101 (DDh) 3 5 19 100 L
LD r,(IY+d) r <- (IY+d) * * X * X * * * 11 111 101 (FDh) 3 5 19 101 H
01 <r> 110 111 A
-- <d> ---
LD (HL),r (HL) <- r * * X * X * * * 01 110 <r> 1 2 7
LD (IX+d),r (IX+d) <- r * * X * X * * * 11 011 101 (DDh) 3 5 19
LD (IY+d),r (IY+d) <- r * * X * X * * * 11 111 101 (FDh) 3 5 19
01 110 <r>
-- <d> ---
LD (HL),n (HL) <- n * * X * X * * * 00 110 110 (36h) 2 3 10
-- <n> ---
LD (IX+d),n (IX+d) <- n * * X * X * * * 11 011 101 (DDh) 4 5 19
LD (IY+d),n (IY+d) <- n * * X * X * * * 11 111 101 (FDh) 4 5 19
00 110 110 (36h)
-- <d> ---
-- <n> ---
LD A,(BC) A <- (BC) * * X * X * * * 00 001 010 (0Ah) 1 2 7
LD A,(DE) A <- (DE) * * X * X * * * 00 011 010 (1Ah) 1 2 7
LD A,(nn) A <- (nn) * * X * X * * * 00 111 010 (3Ah) 3 4 13
-- <nn> --
LD (BC),A (BC) <- A * * X * X * * * 00 000 010 (02h) 1 2 7
LD (DE),A (DE) <- A * * X * X * * * 00 010 010 (12h) 1 2 7
LD (nn),A (nn) <- A * * X * X * * * 00 110 010 (32h) 3 4 13
-- <nn> --
LD A,I A <- I ? ? X 0 X f 0 * 11 101 101 (EDh) 2 2 9
01 010 111 (57h)
LD A,R A <- R ? ? X 0 X f 0 * 11 101 101 (EDh) 2 2 9
01 011 111 (5Fh)
LD I,A I <- A * * X * X * * * 11 101 101 (EDh) 2 2 9
01 000 111 (47h)
LD R,A R <- A * * X * X * * * 11 101 101 (EDh) 2 2 9
01 001 111 (4Fh)
f: Interrupt enable flip-flop copied to P/V.
16-BIT LOAD GROUP
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Mnemonic Symbolic Flags (bit 7-0) Instruction Number Number of Number of Comments
operation S Z . H . V N C opcode of bytes M cycles T states
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LD rr, nn rr <- nn * * X * X * * * 00 rr0 001 3 3 10
-- <nn> --
LD IX, nn IX <- nn * * X * X * * * 11 011 101 (DDh) 4 4 14
LD IY, nn IY <- nn * * X * X * * * 11 111 101 (FDh) 4 4 14
00 100 001 (21h)
-- <nn> --
LD HL,(nn) L <- (nn) * * X * X * * * 00 101 010 (2Ah) 3 5 16
H <- (nn+1) -- <nn> --
LD rr,(nn) rrL <- (nn) * * X * X * * * 11 101 101 (EDh) 4 6 20
rrH <- (nn+1) 01 rr1 011
-- <nn> --
LD IX,(nn) IXL <- (nn) * * X * X * * * 11 011 101 (DDh) 4 6 20
LD IY,(nn) IXH <- (nn+1) * * X * X * * * 11 111 101 (FDh) 4 6 20
00 101 010 (2Ah)
-- <nn> --
LD (nn),HL (nn) <- L * * X * X * * * 00 100 010 (22h) 3 5 16
(nn+1) <- H -- <nn> --
LD (nn),rr (nn) <- rrL * * X * X * * * 11 101 101 (EDh) 4
(nn+1) <- rrH 01 rr0 011
-- <nn> --
LD (nn),IX (nn) <- IXL * * X * X * * * 11 011 101 (DDh) 4 6 20
LD (nn),IY (nn+1) <- IXH * * X * X * * * 11 111 101 (FDh) 4 6 20
00 100 010 (22h)
-- <nn> --
LD SP,HL SP <- HL * * X * X * * * 11 111 001 (F9h) 1 1 6
LD SP,IX SP <- IX * * X * X * * * 11 011 101 (DDh) 2 2 10
LD SP,IY SP <- IY * * X * X * * * 11 111 101 (FDh) 2 2 10
11 111 001 (F9h)
PUSH qq (SP-1) <- qqL * * X * X * * * 11 qq0 101 1 3 11
(SP-2) <- qqH
SP <- SP-2
PUSH IX (SP-1) <- IXL * * X * X * * * 11 011 101 (DDh) 2 4 15
PUSH IY (SP-2) <- IXH * * X * X * * * 11 111 101 (FDh) 2 4 15
SP <- SP-2 11 100 101 (E5h)
POP qq qqL <- (SP) * * X * X * * * 11 qq0 001 1 3 10
qqH <- (SP+1)
SP <- SP+2
POP IX IXL <- (SP) * * X * X * * * 11 011 101 (DDh) 2 4 14
POP IY IXH <- (SP+1) * * X * X * * * 11 111 101 (FDh) 2 4 14
SP <- SP+2 11 100 001 (E1h)
rr: qq:
00 BC 00 BC
01 DE 01 DE
10 HL 10 HL
11 SP 11 AF
EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
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Mnemonic Symbolic Flags (bit 7-0) Instruction Number Number of Number of Comments
operation S Z . H . V N C opcode of bytes M cycles T states
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EX DE,HL DE <-> HL * * X * X * * * 11 101 011 (EBh) 1 1 4
EX AF,AF' AF <-> AF' * * X * X * * * 00 001 000 (08h) 1 1 4
EXX BC <-> BC' * * X * X * * * 11 011 001 (D9h) 1 1 4
DE <-> DE'
HL <-> HL'
EX (SP),HL L <-> (SP) * * X * X * * * 11 100 011 (E3h) 1 5 19
H <-> (SP+1)
EX (SP),IX IXL <-> (SP) * * X * X * * * 11 011 101 (DDh) 2 6 23
EX (SP),IY IXH <-> (SP+1) * * X * X * * * 11 111 101 (FDh) 2 6 23
11 100 011 (E3h)
LDI (DE) <- (HL) * * X 0 X ? 0 * 11 101 101 (EDh) 2 4 16
BC <- BC-1 (1) 10 100 000 (A0h)
DE <- DE+1
HL <- HL+1
LDIR (DE) <- (HL) * * X 0 X 0 0 * 11 101 101 (EDh) 2 5 21 if BC<>0
BC <- BC-1 10 110 000 (B0h) 2 4 16 if BC=0
DE <- DE+1
HL <- HL+1 Repeat until BC=0
LDD (DE) <- (HL) * * X 0 X ? 0 * 11 101 101 (EDh) 2 4 16
BC <- BC-1 (1) 10 101 000 (A8h)
DE <- DE-1
HL <- HL-1
LDDR (DE) <- (HL) * * X 0 X 0 0 * 11 101 101 (EDh) 2 5 21 if BC<>0
BC <- BC-1 10 111 000 (B8h) 2 4 16 if BC=0
DE <- DE-1
HL <- HL-1 Repeat until BC=0
CPI A = (HL) ? ? X ? X ? 1 * 11 101 101 (EDh) 2 4 16
BC <- BC-1 (2) (1) 10 100 001 (A1h)
HL <- HL+1
CPIR A = (HL) ? ? X ? X ? 1 * 11 101 101 (EDh) 2 5 21 if BC<>0 and A<>(HL)
BC <- BC-1 (2) (1) 10 110 001 (B1h) 2 4 16 if BC=0 or A=(HL)
HL <- HL+1 Repeat until BC=0 or A=(HL)
CPD A = (HL) ? ? X ? X ? 1 * 11 101 101 (EDh) 2 4 16
BC <- BC-1 (2) (1) 10 101 001 (A9h)
HL <- HL-1
CPDR A = (HL) ? ? X ? X ? 1 * 11 101 101 (EDh) 2 5 21 if BC<>0 and A<>(HL)
BC <- BC-1 (2) (1) 10 111 001 (B9h) 2 4 16 if BC=0 or A=(HL)
HL <- HL-1 Repeat until BC=0 or A=(HL)
(1) P/V = 0, if result of BC-1 = 0, otherwise P/V = 1
(2) Fz = 1, if A = (HL), otherwise Fz = 0
8-BIT ARITHMETIC AND LOGICAL GROUP
__________________________________________________________________________________________________________________________ Mnemonic Symbolic Flags (bit 7-0) Instruction Number Number of Number of Comments operation S Z . H . V N C opcode of bytes M cycles T states __________________________________________________________________________________________________________________________ ADD A,r A <- A+r ? ? X ? X V 0 ? 10 000 <r> 1 1 4 r: ADD A,n A <- A+n ? ? X ? X V 0 ? 11 000 110 2 2 7 000 C -- <n> --- 001 B ADD A,(HL) A <- A+(HL) ? ? X ? X V 0 ? 10 000 110 1 2 7 010 E 011 D ADD A,(IX+d) A <- A+(IX+d) ? ? X ? X V 0 ? 11 011 101 (DDh) 3 5 19 100 L ADD A,(IY+d) A <- A+(IY+d) ? ? X ? X V 0 ? 11 111 101 (FDh) 3 5 19 101 H 10 000 110 111 A -- <d> --- ADC A,s A <- A+s+CY ? ? X ? X V 0 ? .. 001 ... Please refer to ADD template SUB s A <- A-s ? ? X ? X V 1 ? .. 010 ... Please refer to ADD template SBC A,s A <- A-s-CY ? ? X ? X V 1 ? .. 011 ... Please refer to ADD template AND s A <- A AND s ? ? X 1 X P 0 0 .. 100 ... Please refer to ADD template XOR s A <- A XOR s ? ? X 0 X P 0 0 .. 101 ... Please refer to ADD template OR s A <- A OR s ? ? X 0 X P 0 0 .. 110 ... Please refer to ADD template CP s A - s ? ? X ? X V 1 ? .. 111 ... Please refer to ADD template INC r r <- r+1 ? ? X ? X V 0 * 00 <r> 100 1 1 4 INC (HL) (HL) <- (HL)+1 ? ? X ? X V 0 * 00 110 100 1 3 11 INC (IX+d) (IX+d) <- (IX+d)+1 ? ? X ? X V 0 * 11 011 101 (DDh) 3 6 23 INC (IY+d) (IY+d) <- (IY+d)+1 ? ? X ? X V 0 * 11 111 101 (FDh) 3 6 23 00 110 100 -- <d> --- DEC m m <- m-1 ? ? X ? X V 1 * .. ... 101 Please refer to INC templatePlease note: The V symbol i the flags column for the P/V flag identifies whether an overflow occurred by the operation. The P symbol in the P/V flag identifies parity. V = 1 means overflow, V = 0 means no overflow. P = 1 means the parity of the result is even. P = 0 means that the parity of the result is odd.
__________________________________________________________________________________________________________________________ Mnemonic Symbolic Flags (bit 7-0) Instruction Number Number of Number of Comments operation S Z . H . V N C opcode of bytes M cycles T states __________________________________________________________________________________________________________________________ ADD HL,ss HL <- HL+ss * * X X X * 0 ? 00 ss1 001 1 3 11 ss: 00 BC ADC HL,ss HL <- HL+ss+CY ? ? X X X V 0 ? 11 101 101 (EDh) 2 4 15 01 DE 01 ss1 010 10 HL 11 SP SBC HL,ss HL <- HL-ss-CY ? ? X X X V 1 ? 11 101 101 (EDh) 2 4 15 01 ss0 010 ADD IX,pp IX <- IX+pp * * X X X * 0 ? 11 011 101 (DDh) 2 4 15 pp: 00 pp1 001 00 BC 01 DE ADD IY,qq IY <- IY+qq * * X X X * 0 ? 11 111 101 (FDh) 2 4 15 10 IX 00 qq1 001 11 SP qq: INC ss ss <- ss+1 * * X * X * * * 00 ss0 011 1 1 6 00 BC 01 DE INC IX IX <- IX+1 * * X * X * * * 11 011 101 (DDh) 2 2 10 10 IY 00 100 011 (23h) 11 SP INC IY IY <- IY+1 * * X * X * * * 11 111 101 (FDh) 2 2 10 00 100 011 (23h) DEC ss ss <- ss-1 * * X * X * * * 00 ss1 011 1 1 6 DEC IX IX <- IX-1 * * X * X * * * 11 011 101 (DDh) 2 2 10 00 101 011 (2Bh) DEC IY IY <- IY-1 * * X * X * * * 11 111 101 (FDh) 2 2 10 00 101 011 (2Bh)ROTATE AND SHIFT GROUP
__________________________________________________________________________________________________________________________ Mnemonic Symbolic Flags (bit 7-0) Instruction Number Number of Number of Comments operation S Z . H . V N C opcode of bytes M cycles T states __________________________________________________________________________________________________________________________ +-----------+ | +------+ | RLCA CY <-+-|7 <- 0|<-+ * * X 0 X * 0 ? 00 000 111 (07h) 1 1 4 +- A --+Rotate left circular accumulator
+---------------+ | +------+ | RLA +-CY<-|7 <- 0|<-+ * * X 0 X * 0 ? 00 010 111 (17h) 1 1 4 +- A --+Rotate left accumulator
+-----------+ | +------+ | RRCA +->|7 -> 0|-+-> CY * * X 0 X * 0 ? 00 001 111 (0Fh) 1 1 4 +- A --+Rotate right circular accumulator
+---------------+ | +------+ | RRA +->|7 -> 0|->CY-+ * * X 0 X * 0 ? 00 011 111 (1Fh) 1 1 4 +- A --+Rotate right accumulator
RLC r ---+ ? ? X 0 X P 0 ? 11 001 011 (CBh) 2 2 8 r: | 00 000 <r> 000 C | +-----------+ 001 B RLC (HL) ---+-- | +------+ | ? ? X 0 X P 0 ? 11 001 011 (CBh) 2 4 15 010 E | CY<-+-|7 <- 0|<-+ 00 000 110 011 D | +------+ 100 L | r,(HL),(IX+d),(IY+d) 101 H RLC (IX+d) -+ ? ? X 0 X P 0 ? 11 011 101 (DDh) 4 6 23 111 A RLC (IY+d) -+ ? ? X 0 X P 0 ? 11 111 101 (FDh) 4 6 23 11 001 011 (CBh) -- <d> --- 00 000 110 +---------------+ RL m | +------+ | ? ? X 0 X P 0 ? .. 010 ... Please refer to RLC template +-CY<-|7 <- 0|<-+ +- m --+ +-----------+ RRC m | +------+ | ? ? X 0 X P 0 ? .. 001 ... Please refer to RLC template +->|7 -> 0|-+-> CY +- m --+ROTATE AND SHIFT GROUP, continued
__________________________________________________________________________________________________________________________ Mnemonic Symbolic Flags (bit 7-0) Instruction Number Number of Number of Comments operation S Z . H . V N C opcode of bytes M cycles T states __________________________________________________________________________________________________________________________ +---------------+ RR m | +------+ | ? ? X 0 X P 0 ? .. 011 ... Please refer to RLC template +->|7 -> 0|->CY-+ +- m --+ +------+ SLA m CY <-|7 <- 0|<- 0 ? ? X 0 X P 0 ? .. 100 ... Please refer to RLC template +- m --+ +------+ SRA m +->|7 -> 0|-> CY ? ? X 0 X P 0 ? .. 101 ... Please refer to RLC template | ++ m --+ +---+ +------+ SRL m 0 ->|7 -> 0|-> CY ? ? X 0 X P 0 ? .. 111 ... Please refer to RLC template +- m --+ +--->----+ A | (HL)| +------++ +-----+-+ RLD |7-4|3-0| |7-4|3-0| ? ? X 0 X P 0 * 11 101 101 (EDh) 2 5 18 +------++ ++-+--+-+ 01 101 111 (6Fh) | | | | +<--+ +<-+ Rotate digit left between the accumulator and location (HL) +--->+ +->+ | | | | +-----+-+ ++-+--+-+ RRD |7-4|3-0| |7-4|3-0| ? ? X 0 X P 0 * 11 101 101 (EDh) 2 5 18 +-----+-+ +-----+-+ 01 100 111 (67h) A | (HL)| +---<-----+ Rotate digit right between the accumulator and location (HL)BIT MANIPULATION GROUP
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Mnemonic Symbolic Flags (bit 7-0) Instruction Number Number of Number of Comments
operation S Z . H . V N C opcode of bytes M cycles T states
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BIT b,r Fz <- NOT rb X ? X 1 X X 0 * 11 001 011 (CBh) 2 2 8 r:
01 <b> <r> 000 C
001 B
BIT b,(HL) Fz <- NOT (HL)b X ? X 1 X X 0 * 11 001 011 (CBh) 2 3 12 010 E
01 <b> 110 011 D
100 L
BIT b,(IX+d) Fz <- NOT (IX+d)b X ? X 1 X X 0 * 11 011 101 (DDh) 4 5 20 101 H
BIT b,(IY+d) Fz <- NOT (IY+d)b X ? X 1 X X 0 * 11 111 101 (FDh) 4 5 20 111 A
11 001 011 (CBh)
-- <d> ---
01 <b> 110 b:
000 0
001 1
SET b,r rb <- 1 * * X * X * * * 11 001 011 (CBh) 2 2 8 010 2
11 <b> <r> 011 3
100 4
SET b,(HL) (HL)b <- 1 * * X * X * * * 11 001 011 (CBh) 2 4 15 101 5
11 <b> 110 110 6
111 7
SET b,(IX+d) (IX+d)b <- 1 * * X * X * * * 11 011 101 (DDh) 4 6 23
SET b,(IY+d) (IY+d)b <- 1 * * X * X * * * 11 111 101 (FDh) 4 6 23
11 001 011 (CBh)
-- <d> ---
11 <b> 110
RES b,r rb <- 0 * * X * X * * * 11 001 011 (CBh) 2 2 8
10 <b> <r>
RES b,(HL) (HL)b <- 0 * * X * X * * * 11 001 011 (CBh) 2 4 15
10 <b> 110
RES b,(IX+d) (IX+d)b <- 0 * * X * X * * * 11 011 101 (DDh) 4 6 23
RES b,(IY+d) (IY+d)b <- 0 * * X * X * * * 11 111 101 (FDh) 4 6 23
11 001 011 (CBh)
-- <d> ---
10 <b> 110
Please note: The bit to be tested by the BIT instruction is first inverted
before copied to Fz, ie. Fz = 1 if the corresponding bit is zero. Fz =
0 if the corresponding bit is 1.
__________________________________________________________________________________________________________________________ Mnemonic Symbolic Flags (bit 7-0) Instruction Number Number of Number of Comments operation S Z . H . V N C opcode of bytes M cycles T states __________________________________________________________________________________________________________________________ JP nn PC <- nn * * X * X * * * 11 000 011 (C3h) 3 3 10 -- <nn> -- JP cc,nn if condition true * * X * X * * * 11 <cc> 010 3 3 10 cc: condition PC <- nn 000 NZ not zero else 001 Z zero continue 010 NC not carry 011 C carry 100 PO parity odd 101 PE parity even 110 P sign posit. 111 M sign nega. JR e PC <- PC+e * * X * X * * * 00 011 000 (18h) 2 3 12 <e-2> JR C,e if C = 0, continue * * X * X * * * 00 111 000 (38h) 2 2 7 condition not met else, PC <- PC+e <e-2> 2 2 12 condition met JR NC,e if C = 1, continue * * X * X * * * 00 110 000 (30h) 2 2 7 condition not met else, PC <- PC+e <e-2> 2 2 12 condition met JR Z,e if Z = 0, continue * * X * X * * * 00 101 000 (28h) 2 2 7 condition not met else, PC <- PC+e <e-2> 2 2 12 condition met JR NZ,e if Z = 1, continue * * X * X * * * 00 100 000 (20h) 2 2 7 condition not met else, PC <- PC+e <e-2> 2 2 12 condition met DJNZ,e B <- B-1 * * X * X * * * 00 010 000 (10h) 2 2 8 if B = 0 if B = 0, continue <e-2> 2 2 13 if B <> 0 else, PC <- PC+e JP (HL) PC <- HL * * X * X * * * 11 101 001 (E9h) 1 1 4 JP (IX) PC <- IX * * X * X * * * 11 011 101 (DDh) 2 2 8 11 101 001 (E9h) JP (IY) PC <- IY * * X * X * * * 11 111 101 (FDh) 2 2 8 11 101 001 (E9h)e represents a 2. complement 8-bit integer which defines a relative jump in the range [-126; 129].
__________________________________________________________________________________________________________________________ Mnemonic Symbolic Flags (bit 7-0) Instruction Number Number of Number of Comments operation S Z . H . V N C opcode of bytes M cycles T states __________________________________________________________________________________________________________________________ CALL nn (SP-1) <- PCh * * X * X * * * 11 001 101 (CDh) 3 5 17 (SP-2) <- PCl -- <nn> -- SP <- SP-2 PC <- nn CALL cc,nn if not cc, continue * * X * X * * * 11 <cc> 100 3 5 10 if cc is false else, CALL nn -- <nn> --- 3 5 17 if cc iss true RETI return from * * X * X * * * 11 101 101 (EDh) 2 4 14 cc: condition interrupt 01 001 101 (4Dh) 000 NZ not zero 001 Z zero RETN return from non- * * X * X * * * 11 101 101 (EDh) 2 4 14 010 NC not carry maskable interrupt 01 000 101 (45h) 011 C carry 100 PO parity odd RET PCl <- (SP) * * X * X * * * 11 001 001 (C9h) 1 3 10 101 PE parity even PCh <- (SP+1) 110 P sign posit. SP <- SP+2 111 M sign nega. RET cc if not cc, continue * * X * X * * * 11 <cc> 000 1 1 5 if cc is false else, RET 1 3 11 if cc is true RST p (SP-1) <- PCh * * X * X * * * 11 <t> 111 1 3 11 t: p: (SP-2) <- PCl 000 00h SP <- SP-2 001 08h PCh <- 0 010 10h PCl <- p 011 18h 100 20h 101 28h 110 30h 111 38hINPUT AND OUTPUT GROUP
__________________________________________________________________________________________________________________________ Mnemonic Symbolic Flags (bit 7-0) Instruction Number Number of Number of Comments operation S Z . H . V N C opcode of bytes M cycles T states __________________________________________________________________________________________________________________________ IN A,(n) A <- (n) * * X * X * * * 11 011 011 (DBh) 2 3 11 n to A0 - A7 -- <n> --- Acc to A8 - A15 IN r,(C) r <- (C) ? ? X ? X P 0 * 11 101 101 (EDh) 2 3 12 C to A0 - A7 if r = 110, only flags is affected 01 <r> 000 B to A8 - A15 INI (HL) <- (C) X ? X X X X 1 * 11 101 101 (EDh) 2 4 16 C to A0 - A7 B <- B-1 (1) 10 100 010 (A2h) B to A8 - A15 HL <- HL+1 INIR (HL) <- (C) X 1 X X X X 1 * 11 101 101 (EDh) 2 5 21 (B<>0) C to A0 - A7 B <- B-1 10 110 010 (B2h) 2 4 16 (B=0) B to A8 - A15 HL <- HL+1 Repeat until B=0 IND (HL) <- (C) X ? X X X X 1 * 11 101 101 (EDh) 2 4 16 C to A0 - A7 B <- B-1 (1) 10 101 010 (AAh) B to A8 - A15 HL <- HL-1 INDR (HL) <- (C) X 1 X X X X 1 * 11 101 101 (EDh) 2 5 21 (B<>0) C to A0 - A7 B <- B-1 10 111 010 (BAh) 2 4 16 (B=0) B to A8 - A15 HL <- HL-1 Repeat until B=0 OUT (n),A (n) <- A * * X * X * * * 11 010 011 (D3h) 2 3 11 n to A0 - A7 -- <n> --- Acc to A8 - A15 OUTI (C) <- (HL) X ? X X X X 1 * 11 101 101 (EDh) 2 4 16 C to A0 - A7 B <- B-1 (1) 10 100 011 (A3h) B to A8 - A15 HL <- HL+1 OTIR (C) <- (HL) X 1 X X X X 1 * 11 101 101 (EDh) 2 5 21 (B<>0) C to A0 - A7 B <- B-1 10 110 011 (B3h) 2 4 16 (B=0) B to A8 - A15 HL <- HL+1 Repeat until B=0 OUTD (C) <- (HL) X ? X X X X 1 * 11 101 101 (EDh) 2 4 16 C to A0 - A7 B <- B-1 (1) 10 101 011 (ABh) B to A8 - A15 HL <- HL-1 OTDR (C) <- (HL) X 1 X X X X 1 * 11 101 101 (EDh) 2 5 21 (B<>0) C to A0 - A7 B <- B-1 10 111 011 (BBh) 2 4 16 (B=0) B to A8 - A15 HL <- HL-1 Repeat until B=0(1) If the result of B-1 = 0, then Fz = 1, otherwise Fz = 0.
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